Because the leakage current of a digital circuit depends on the states of the circuit's logic gates, assigning a minimum leakage vector (MLV) for the primary inputs and the flip-flops' outputs of the circuit that operates in the sleep mode is a popular technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn vector controller, our technique can take this overhead into account. Ignoring this overhead during solution space exploration may bring a side effect that is misrecognizing a non-optimal solution as an optimal one. Experimental results show that our heuristic algorithm can reduce the leakage current up to 59.5% and can find the optimal solutions on most of the small MCNC benchmark circuits. Moreover, the required CPU time of our probability-based program is significantly less than that of a random search program.

We have studied the electrical and breakdown characteristics of 5 nm-thick HfSiOxNy (Hf/(Hf + Si)=0.43, nitrogen content=4.5-17.8 at.%) in Al-gate and NiSi-gate capacitors. For Al-gate capacitors, the flat-band shift due to positive fixed charges increases with the nitrogen content in the dielectric layer. In contrast, for NiSi-gate capacitors, the flat band is almost independent of the nitrogen content, which is presumably controlled by the quality of the interface between NiSi and the dielectric layer. The leakage current markedly increases with nitrogen content. Correspondingly, although the time-to-soft breakdown, tSBD, gradually decreases with increasing nitrogen content, the charge-to-soft breakdown, QSBD, increases with the nitrogen content. For Al-gate capacitors, the Weibull slope of time-dependent dielectric breakdown (TDDB) under constant voltage stress (CVS) remains constant at 2 for a nitrogen content of up to 12.5 at.% and then decreases to unity at 17.8 at.%. This must be a condition critical to the formation of the percolation path for breakdown. In contrast, for NiSi gate capacitors, a Weibull slope smaller than unity was obtained, suggesting that structural inhomogeneity, involving defect generation, is introduced during the NiSi gate fabrication, but this negative impact is reduced with nitrogen incorporation.

The physical origin of stress-induced leakage currents (SILC) in ultra-thin SiO2 films is described. Assuming a two-step trap-assisted tunneling process accompanied with an energy relaxation process of trapped electrons, conditions of trap sites which are origin of SICL are quantitatively found. It is proposed that the trap site location and the trap state energy can be explained by a mean-free-path of hole in SiO2 films and an atomic structure of the trap site by the O vacancy model.

To drastically reduce the dynamic power (PAT) and the leakage power (PST) of the CMOS MPEG4/H.264 motion estimation (ME) circuits, several power reduction techniques were developed. They were circuit architectures, which were able to reduce the supply voltages (VDD) and numbers of logic gates of not only the whole circuit but the critical path, a fast motion estimation algorithm, and a leakage current reduction circuit. A 0.18-µm CMOS ME circuit has been fabricated by adopting those techniques. At a clock frequency of 160 MHz and VDD of 1.25 V, PAT decreased to 75.9 µW, which was 5.35% that of a conventional ME circuit. PST also decreased to 0.82 nW, which was 3.93% that of the conventional ME circuit.

A new multiple-valued current-mode (MVCM) logic circuit using substrate bias control is proposed for low-power VLSI systems at higher clock frequency. Since a multi-level threshold value is represented as a threshold voltage of an MOS transistor, a voltage comparator is realized by a single MOS transistor. As a result, two basic components, a comparator and an output generator in the MVCM logic circuit can be merged into a single MOS differential-pair circuit where the threshold voltages of MOS transistors are controlled by substrate biasing. Moreover, the leakage current is also reduced using substrate bias control. As a typical example of an arithmetic circuit, a radix-2 signed-digit full adder using the proposed circuit is implemented in a 0.18- µm CMOS technology. Its dynamic and static power dissipations are reduced to about 79 percent and 14 percent, respectively, in comparison with those of the corresponding binary CMOS implementation at the supply voltage of 1.8 V and the clock frequency of 500 MHz.

The process mapping of the ALD process of HfO2 using HfCl4 and H2O is reported. A thickness uniformity better than 3% was achieved over a 300 mm-wafer at a deposition rate of 0.52 Å/cycle. Usually, H2O purge period is set less than 10 sec to obtain reasonable throughput; however, the amounts of residual impurities (Cl, H) found to be in the order of sub%, and these impurities are piled up near the HfO2/Si interface. In order to reduce the piled up impurities, we proposed a 2-step deposition in which purge period for initial 10-20 cycles was set to be 90 sec and that for remaining cycles was usual value of 7.5 sec. The leakage current is reduced to 1/10 by using this 2-step deposition.

In order to clarify the mechanism of gate leakage in AlGaN/GaN heterostructure field effect transistors (HFETs), temperature (T)-dependent current-voltage (I-V) characteristics of Ni/n-AlGaN Schottky contact were measured in detail. Large deviations from the thermionic emission transport were observed in I-V-T behavior with anomalously large reverse leakage currents. An analysis based on the thin surface barrier (TSB) model showed that the nitrogen-vacancy-related near-surface donors play a dominant role in the leakage through the AlGaN Schottky interface. As a practical scheme for suppressing the leakage currents, use of an insulated gate (IG) structure was investigated. As the insulator, Al2O3 was selected, and an Al2O3 IG structure was formed on the AlGaN/GaN heterostructure surface after an ECR-N2 plasma treatment. An in-situ XPS analysis exhibited successful formation of an ultrathin stoichiometric Al2O3 layer which has a large conduction band offset of 2.1 eV at the Al2O3/Al0.3Ga0.7N interface. The fabricated Al2O3 IG HFET achieved pronounced reduction of gate leakage, resulting in the good gate control of drain currents up to VGS = +3 V. The maximum drain saturation current and transconductance were 0.8 A/mm and 120 mS/mm, respectively. No current collapse was observed in the Al2O3 IG-HFETs, indicating a remarkable advantage of the present Al2O3-based insulated gate and passivation structure.

High-temperature stability of copper (Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) was investigated. Samples were annealed at various temperatures to monitor the changes on device performances. Current-voltage performance such as drain-source current, transconductance, threshold voltage and gate leakage current has no obvious degradation up to annealing temperature of 500 and time of 5 minutes. Also up to this temperature, no copper diffusion was found at the Cu and AlGaN interface by secondary ion mass spectrometry determination. At annealing temperature of 700 and time of 5 minutes, device performance was found to have degraded. Gate voltage swing increased and threshold voltage shifted due to Cu diffusion into AlGaN. These results indicate that the Schottky contact and device performance of Cu-gate AlGaN/GaN HEMT is stable up to annealing temperature of 500. Cu is a promising candidate as gate metallization for high-performance power AlGaN/GaN HEMTs.

Problems concerning a phase-locked loop (PLL) fabricated by a deep-sub-micron process were investigated, and a high-speed self-calibration technique for tuning a voltage-controlled oscillator (VCO) frequency range automatically was developed. The self-calibration technique can measure VCO frequency in short time by comparing intervals between a PLL reference and a VCO output. Furthermore, a loop-filter bypassing method was also used to change the calibration frequency in short time. At 0.7 V and 200 MHz, the prototype PLL has a calibration time of 1.4 µs and a total settling time of 10 µs, which are adequate for microprocessor applications. Moreover, the PLL has a cycle-to-cycle jitter of 142 ps and a power consumption of 470 µW.

We have investigated fabricating fine active regions by tuning process condition of conventional LOCOS for the fabrication of the gate width 100 nm MOSFET. Considering the lowering in fluidity of silicon dioxide, oxidation temperature was changed to 900 which is lower than conventional 1000. In addition active region shape was modified to utilize vertical stress due to nitride elastic force. As a result, 75 nm width fine active region was successfully fabricated. Though lowering of the oxidation temperature tends to increase stress, junction leakage current and gate oxide reliability showed no degradation. On the other hand, PSL (Poly-Si Sidewall LOCOS) gave rise to degradation in the electrical properties by the stress. Using the LOCOS process, we have fabricated the MOSFETs with the fine active regions.

We have developed 100 nm node CMOS technology, consisting of a 65 nm gate length and a 1.6 nm gate oxide thickness. The major transistor design issue is how to maintain drive current at supply voltage of only 1.0 V, while suppressing standby leakage current to a practical level for system-on-a-chip applications. In order to obtain thinner electrical equivalent oxide thickness with well-suppressed gate leakage current, we have adopted radical nitridation and poly-SiGe. We have also utilized low-energy ion-implantation, low-temperature CVD, and spike RTA technology to overcome the short channel effect. With supply voltage of 1.0 V, our generic transistor shows the drive current of 520/196 µA/µm with the off current of 0.5 nA/µm. We also designed high-speed (Ioff=5 nA/µm), ultrahigh-speed (Ioff=30 nA/µm) transistors, and low-standby power (Ioff=5 pA/µm), all of which can be deployed on the same chip.

We have designed the Half Adder (HA) circuit and the Carry Save Serial Adder (CSSA) circuit based on pipeline architecture. Our HA has the structure of a two-stage pipeline and consists of 160 Josephson Junctions (JJs). Our CSSA has the structure of a four-stage pipeline with a feedback loop and consists of 360 JJs. These circuits were fabricated by the NEC standard process. There are two issues which should be considered in the design. One is parameter spreads generated by the fabrication process and the other is leakage currents between the gates. We have introduced a parameter optimization method to deal with the parameter spreads. We have also inserted three stages of JTLs to reduce leakage currents. We have experimentally confirmed the correct operations of these circuits. The obtained bias margins were 33.1% for the HA and 24.6% for the CSSA.

Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

Surface morphology and piezo response on SBT films were simultaneously measured by scanning probe microscopy. In a sample that had many short-circuited capacitor pads, some curious structures were observed on the SBT film surface. The piezo image partially did not correspond with the AFM image. Some specific grains were revealed to be piezo defects. Also observed were some smaller grains with flat surface, which showed good ferroelectricity. Next, we carried out simultaneous measurements of surface morphology and leakage current. The scanning at an intentionally high voltage was repeated until the leakage points were found. We found the leakage points, which were on some large grains, not at grain boundaries or on the flat smaller grains. In another SBT film derived from an unrefined source, many ferroelectric defects were observed despite there being no curious structures on the surface. Purity has an important bearing on the ability to avoid these defects. Thus, these nanoscopic investigations would greatly facilitate understanding of the mechanisms responsible for problems and enable optimization of the process conditions in device fabrication.

Random modulation refers to the changing of the MOSFET threshold voltage cell by cell. This paper claims it is essential in sub-2-V CMOS design because it reduces the sub-threshold leakage current even in the active and sleep modes as well as in the stand-by mode. We found that a gradated modulation scheme, which gradually changes the ratio of low- Vth cells according to the path-delay, is the best approach. To achieve the minimal leakage current, the way of determining the optimum pair of threshold voltages is also described. Experimental results for microprocessor show that gradated modulation reduces sub-threshold leakage current by 75% to 90% compared to conventional single-low-threshold voltage design without degrading the performance of the circuits.

We have proposed and fabricated a new poly-Si TFT employing the selectively doped regions in the active layer. In the proposed poly-Si TFTs, the selectively doped regions where doping concentration is identical to that of the source/drain, reduce the effective channel length during the on-state. Under the off-state, the selectively doped regions may reduce the lateral electric field induced near the drain and reduce the leakage current considerably. The experimental data of the proposed TFT exhibit high on-current, low leakage current and low threshold voltage. The fabrication of the proposed TFT is rather simple; the required steps for the proposed TFT are reduced because high dosage ion-implantation for the source/drain and the selectively doped regions is performed simultaneously prior to excimer laser irradiation step.

Anomalous leakage current which flows between source and drain in thin film SOI MOSFET's is investigated. It is confirmed that the leakage current is caused by enhanced diffusion of the source/drain dopants along the LOCOS-induced crystal defects. Stress analysis by 2D simulation reveals that thinning a buried-oxide effectively suppresses deformation of an SOI film associated with over-oxidation during LOCOS. It is experimentally confirmed that using a SIMOX substrate which has a thinner buried-oxide causes no noticeable deformation of the SOI film nor anomalous leakage current.

An elastic-Vt CMOS circuit is proposed which facilitates both high speed and low power consumption at low supply voltages. This circuit permits fine-grain power control on each multiple circuit block composing a chip, and it is not sensitive to design factors as device-parameter deviations or operating-environment variations. It also does not require any such additional fabrication technology as triple-well structure or multi-threshold voltage. The effectiveness of the circuits design was confirmed in applying it to specially fabricated 16-bit adders and 4-kb SRAMs based on 1. 5-V, 0. 35- µm CMOS technology.

This paper describes the new write/erase operation methods in order to improve the read disturb characteristics for Flash EEPROM cells which are written by channel hot electron injection and erased by F-N tunneling emission from the floating gate to the substrate. The new operation methods is either applying a reverse polarity pulse after each erase pulse or applying a series of shorter erase pulses instead of a long single erase pulse. It is confirmed that by using the above operation methods, the leakage current can be suppressed, and then the read disturb life time after 105 cycles write/erase operation is more than 10 times longer in comparison with the conventional method. This memory cell by using the proposed write/erase operation method has superior potential for application to 256 Mbit Flash memories as beyond.

This paper describes a new reduction mechanism of the stress induced leakage current that is induced by step tunneling of electrons through the step tunneling sites. The concept of this mechanism is based on the deactivation of step tunneling sites for thin oxide. It is verified that the deactivation is electrically realized by the injected electrons int the sites. It is because the step tunneling probability of electrons though the deactivated sites is suppressed, since the electron capture cross section of the neutralized deactivation sites becomes extremely low. The deactivation scheme is as follows: (1) The deactivation of tunneling sites can be realized that the tunneling sites trapped holes change to neutralized tunneling sites due to electrons injection. (2) The injected electron can deactivate the activation tunneling sites only under energy level than the energy level of the injected electrons. It is shown that the above reduction phenomenon can be quantifiably with formulation. These results are very important for high reliable thin oxide films and for high performance ULSI.